ABSTRACTS

Wed 10:50Thorsten MeyerKeynote: Megatrends – Impact on Package Technologies

Megatrends have strong transformative power, which can change economy, company landscapes and the society. With an ongoing move to digitalization in many areas of daily life, the semiconductor industry is also strongly influenced by Megatrends. In parallel, a major trend in semiconductors is the transfer of technical challenges from the chip to the package. Advanced packaging is becoming more and more part of the scaling and the functionality roadmaps.

The presentation will introduce to selected megatrends and explain the new challenges and solutions for the packaging industry by practical examples.

Wed 11:30 Christian Boit Contactless Fault Isolation for Nanoscale Low Power Technologies on Chip and System

Contactless Fault Isolation (CFI) on Chip Level for Technologies of 10nm feature size and smaller is still possible with easy-to-use optical interaction when photon energies exceed 1.1 eV. Electro-optical voltage probing techniques are sensitive in low power regime. An obvious challenge is sample thinning, but photocurrents generated by light sources might influence the performance of devices under investigation. Here, photon emission (PE) is presented as interesting candidate for supplement. PE, if detected in wavelength regime of 1.5µm and higher, regains sensitivity for low power and offers interesting information, especially if spectrally evaluated. It may become a bridge to system level CFI as well.

Wed 11:50Kristof J. P. Jacobs
Defect Localization in 3-D TSV Structures by Differential Light-Induced Capacitance Alteration

We present results on differential light-induced capacitance alteration (LICA) as a non-destructive method for localizing metal interconnection line defects in through-silicon-via (TSV) structures used for three-dimensional (3-D) integration technology. Due to the photosensitive silicon depletion capacitance, observation of TSV photocapacitance response enables non-destructive two-dimensional (2-D) visualization of metallization line ruptures. The measurement is performed by scanning a focused laser beam over the surface of the structure and sensing the photoinduced change in electrical capacitance using a differential capacitance measurement set-up. We demonstrate application of the technique on an on open failed 5×50 µm via-middle TSV chain structure and reveal the location of the open metallization rupture.

Wed 13:40
Sebastian Brand, Frank AltmannNew Approaches for 3D LIT by Time Resolved Temperature Response Analysis

Lock-in thermography (LIT) has widely gained acceptance as a standard technique in non-destructive defect localization. Due to its high sensitivity to thermally active electrical defects LIT is capable of inspection through optically opaque materials, allowing detection of resistive defects in fully packaged devices. By investigating the time-resolved temperature response (TRTR) and analysis of their spectral content the locally resolved phase-shift to frequency characteristics can be obtained. The spectral phase characteristics of the TRTR is highly correlated to the axial (z) position of a thermal source, e.g. a resistive defect [1, 2] enabling a non-destructive 3D-localization of electrical defects. The accuracy and resolution of the z-position depend on the precision of the phase-shift estimates but also on the thermal parameters of the ambient material system which may promote thermal spreading. For the analysis of the spectral distribution of the phase-shift as a function of the lock-in frequency the devices are excited electrically by a square-shaped signal in an “on-off” sequence. This signal shape allows for the simultaneous acquisition and analysis of the harmonics and thus the investigation of multiple frequencies leading to a shorter time-to-results parameter. The current paper presents the method of spectral analysis in LIT and illustrates the benefits time-resolved acquisition and signal analysis [3] provides for imaging resolution and 3D-localization.

Wed 14:00Antoine Reverdy

Non Destructive Open Fault Localization on Complex Packages Using EOTPR Technique

Localizing defects (and, particularly, open defects) at package level is becoming a real challenge for Failure Analysis Laboratories due to package diversity and complexity. One of the well-known approaches to address this set of problems within the device is the Time Domain Reflectometry (TDR). The main limitation of this technique is the lack of resolution and sensitivity. Electro Optical Terahertz Pulse Reflectometry (EOTPR) is overcoming these limitations by using a photoconductive terahertz pulse generation and detection technology, resulting in a system with: (i) high measurement bandwidth, (ii) extremely low time base jitter, and (iii) high time base resolution and range with greater sensitivity. In this paper we will present some case studies on various types of devices on which EOTPR approach provided interesting results.

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Wed 14:20
Markus Sauter, Zhongling QianIC Defect Localization by Gated and Spectral Resolved Photo Emission Microscopy

Gated imaging of dynamic photoemission (GI-PEM) can be realized in an economically efficient way using a near-infrared InGaAs image intensifier. Various problems like voltage spiking, ESD, latch-up or power-up behaviour can be addressed. Combining GI-PEM with a transmission grating gives additionally spectral information (SPI-PEM). First results for dynamical photoemission with spectral resolution of a power MOSFET under TLP stress will be presented. Investigations of the dynamical photoemission and its spectral behaviour promises detailed understanding of the physical process and hence performance improvements.

Wed 14:40Pascal LimbeckerCatching Nano-Scaled Defects with PFA – Limits of Localization Methods

With every new technology node the line width and space of the copper interconnect system is getting smaller and smaller. Hence, the risk that nanometer scaled particles cause electrical shorts or opens increases. We developed a test wafer, populated with specifically designed test structures, to catch these defects early in the production, instead of waiting for electrical test data of finished real products, where PFA work needs much higher effort. While opens in long metal line test structures are easy to catch with voltage contrast, the localization of high resistive leakage paths, with currents in the lower pA-range, shows the OBIRCH (Optical Beam Induced Resistance Change) method at its limits. In this presentation we like to show options to improve the OBIRCH scan parameters and a strategy on how to localize failures on large uniform test structures. Therefore, electron beam carbon markers are deposited at high magnifications. Also, a new method will be presented to numerically calculate the location of a short path, when OBIRCH is not able to detect a useful signal. For a clear interpretation of the failure mode, meaningful SEM or TEM images of the defect are needed. In a case where a tiny short path is not visible in the TEM bright and dark field images, we also present how we optimized TEM/EDS parameters and the advantage of planar instead of cross section TEM sample preparation.

Wed 16:00
Steven RandolphCombined Femtosecond Laser and Plasma DualBeam for In-situ Failure and Materials Analysis

The extraordinary removal rate and athermal nature of the femtosecond laser offers a potential bridge in the spatial divide between plasma FIB (PFIB) and mechanical polishing while minimizing risk of thermal damage.  Combination of high resolution SEM, high current PFIB, and an ultrafast femtosecond laser at a single coincidence point on a eucentric axis uniquely allows for rapid failure analysis, depackaging, and automated 3D characterization suitable for electronics, display, and materials problems.  In many cases, laser cutting alone produces remarkable results.  For more targeted  problems, rapid switching to PFIB allows for finer polishing of the large areas exposed by the laser. Here we discuss the hardware as well as application of the system to large scale semiconductor device analysis, organic device analysis, 3D materials characterization, and depackaging operations.

Wed 16:20
Michael GrimmLaser-Micromachining for Failure Analysis: from TEM Sample Preparation to Large Area SEM Inspection

For complex high density SiP and new interconnect technologies like TSV, TEV and μ-bump located defect sites have to be accessed for physical failure analysis. Standard mechanically grinding and polishing techniques are very limited in precision and standard FIB milling is much too slow to prepare the required cross sections for SEM and TEM analysis of buried interfaces in multi-chip designs and interconnects with only several μm diameter and high aspect ratios.

In order to solve this task in a fast and precise way different gentle laser processes are introduced for pre-preparation of the samples prior to the final polishing step by FIB or broad ion beam. We will show how different workflows using laser technologies can speed up the failure preparation process very efficient such as:

  • Preparation of TEM lamellas out of complex devices
  • Cross sectioning by box milling or line cutting for high resolution SEM analysis
  • Semiconductor back thinning for failure visualization by infrared microscopy

This work has been partly performed in the project SAM3, where the German partners are funded by the German Bundesministerium für Bildung und Forschung (BMBF) under contract 16ES0347 and the French partners by the French Ministry for Industry and Economy. SAM3 is a joint project running in the European EUREKA EURIPIDES and CATRENE programs.

Wed 16:40
Jiaqi TangApplications of MIP Decapsulation in Device Quality Control and Failure Analysis

Successful device quality control and failure analysis depends on reliable sample preparation methods. Halogen-free Microwave Induced Plasma (MIP) decapsulation has proven to be able to preserve critical structures on the device while maintaining the electrical functionality. During failure analysis MIP has proven to preserve delicate evidence that would otherwise have been lost using conventional decapsulation methods.

This talk presents several MIP case studies collected from different users covering fragile bond wire and bond pad, backside analysis, transparent mold compound, gallium arsenide, multi-die decapsulation on PCB and field return failure Analysis.

Wed 17:00
Michael BattistaExtreme Backside Thinning for Laser Voltage Probing

Extreme backside thinning of the silicon substrate of advanced integrated circuits (ICs) is intended to meet the resolution challenges of flip chip optical debug tools working on shrinking semiconductor process nodes. The silicon substrate of the IC is transparent to near infrared wavelengths, but as the silicon is ultra-thinned, shorter wavelengths in the visible regime can be employed to gain improved optical resolution. This paper focuses on extreme backside thinning of the IC substrate to 1-3 ums of remaining silicon thickness (RST), using high accuracy optical metrology for measurement feedback and a highly accurate side grinding methodology.

Wed 17:20
Pascal GounetPlasma-FIB Delayering and Nanoprobing

On our latest silicon technologies, planar deprocessing is done by the meaning of dry & wet chemistries for thick metal levels. For thin metal ones semi-automated or manual polishing is preferred. Control is done under optical microscope at the beginning. Then with a SEM in order to be able to find very small features. Drawback is “round trips” between polishing system and SEM. Idea was to find a way to take advantage of a FIB-SEM system in order to do deprocessing with FIB and observations with SEM into the same System.

Thur 08:30Ingo Schulmeyer3D Analysis of Advanced Logic and Memory Devices

Semiconductor devices have firmly moved in to an era where scaling is driven by 3D architectures. However, most of the inspection technologies in today’s labs were developed for 2D devices and are not always sufficient to deal with 3D structures. In recent years, FIB tomography has rapidly evolved to a common and robust microscope technology which is used in numerous disciplines of materials and life sciences. However, in the investigation of semiconductor devices, FIB-tomography is still a small niche, that is not used widely. One reason for that has been the achievable volumetric resolution (i.e. voxel size) that lies typically between 5 to 10 nm.  Another point to consider is that a higher resolution will limit the volume that can be analyzed due to the increased acquisition time. Typical tomography workflows require a sequential imaging and milling procedure. In some cases it is even required to move the sample between milling and imaging positioning in each process cycle to obtain a reasonably high resolution. In our approach, we apply milling and imaging at the same time without compromising resolution. This speeds up not only the acquisition time by at least a factor of 2, but it also allows real-time process control of the milling process. To get reasonable information out of the sequentially acquired SEM images in tomography, an isotropic voxel size is desirable. For modern SEMs it is no problem to achieve lateral resolutions below 1nm. That means that the limiting factor for achieving small isotropic voxels is the thickness of the slices that are removed with the focused ion beam. Another issue when milling thousands of slices is the homogeneity of the thickness. Due to thermal drift, the ion beam shows variations over time, which affects the slice thickness. To allow accurate segmentation and analysis of the 3D data it is important to understand and compensate for these variations. We will show how FIB-Tomography can be used for different tasks in Failure Analysis and 3D process control on VNAND and Fin-FET devices and how it can provide additional information to conventional methods.

Thur 08:50
Miriam UngerNanoscale AFM-IR Spectroscopy for Failure Analysis of Electronic Devices

Characterizing nanoscale surface contaminations in interconnects and circuitries has become a pivotal issue in the test and failure analysis in the semiconductor industry due to the systematic shrinking of the device size. Continuous development in the process technology/engineering led to the fabrication of semiconductor devices with sub-µm feature resolution, which in turn demands high resolution analytical tools for characterization. Scanning Electron Microscopy coupled with Energy Dispersive X-ray spectroscopy (SEM/EDX) is routinely used in surface analysis and offers sub-µm spatial resolution with semi-quantitative elemental analysis. Although, the elemental analysis offers useful chemical insight into the surface defects and contamination, it is fairly limited to inorganics. Infrared (IR) spectro/microscopy, on the other hand provides superior results identifying organic materials. However, the traditional IR spectro-microscopic defect analysis methods offer the diffraction limited detection resolution only up to 3-10 µm or larger.

In contrast, nanoscale IR spectroscopy is an emerging technique that combines high spatial resolution of an AFM with reliable chemical analysis capability of IR spectroscopy (AFM-IR). One method of nanoscale infrared spectroscopy, photothermal atomic force microscope based infrared spectroscopy (AFM-IR) directly detects IR radiation absorbed by the sample using the AFM probe tip to sense thermal expansion. This thermal expansion depends primarily on the absorption coefficient of the sample and is largely independent of other optical properties of the AFM tip and the sample. Recently, we extended the capability of AFM-IR technology to facilitate higher sensitivity, spatial resolution and robust statistical analysis to broaden the range of applications in failure analysis of electronic devices. This presentation will describe the underlying technology including their recent advances and will also highlight numerous applications of nanoscale spectroscopy and chemical imaging.

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Thur 09:10
Christian RettigCase Study: Impact of ECU Housing on Al Bond Wire Degradation in D2PAK Devices

To ensure the level of reliability which is required by the automotive industry, electronic components have to pass dedicated qualification procedures before they are released for the use in automotive electronic control units (ECUs). The automotive industry suppliers consistently optimize their components to withstand these automotive specific field loads. In the case at hand a common and well developed D2PAK passed all component release procedures. Even extended stress tests on component level were passed. A temperature cycle stress on ECU level led to electrical fails of this electronic device. In this talk the observed failure mode will be discussed and the development of a proper stress test to provoke this failure mechanism on component level will be shown. Two remedies to avoid the shown degradation mechanism will be discussed.

Thur 09:30
Motoki Eto Newly Developed High Reliability Palladium Coated Cu Wire for Automotive Application

Au has been mainly used as a material of the bonding wire. In the past several years, Au has been replaced with Cu in the field of LSI devices. Recently, needs for replacing Au wire with Cu wire is increasing also in automotive devices. Automotive devices require higher bond reliability than LSI devices. In this study, bond reliability was investigated with bare Cu, Au-Pd coated copper (APC) and new Au-Pd-coated copper (new-APC) wire in detail. New-APC wire has higher concentration of added element than APC wire. New-APC wire has higher reliability at higher temperature and higher humidity. 

Thur 09:50
Daniel GoranCrystal Orientation Mapping and Imaging Using On-Axis Transmission Kikuchi Diffraction (TKD) Technique in the SEM

Since its introduction a few years ago, TKD in SEM has attracted a lot of attention due mainly to its improved spatial resolution which can be up to one order of magnitude better compared to EBSD. We have developed a unique hardware configuration which “replicates” the TEM sample-detector geometry, i.e. the detector is placed underneath the electron transparent sample thus collecting the signal where is strongest and with the lowest gnomonic projection distortions. I will describe the advantages of our TKD approach and support my statements with experimental results. I would also like to present a few application examples of dark field / bright field imaging capabilities which are built-in our TKD hardware solution.

Thur 10:50
Markku TilliKeynote: C-SOI as a New Generation MEMS Sensor Platform, Current Status and Challenges

SOI wafers with thick device layers have gained popularity in various MEMS designs, especially in inertial sensors, but also other devices, like pressure sensors, resonators, ultrasound transducers and micro mirrors benefit of the SOI structure. It was realized early, that device manufacturing could be greatly simplified if the SOI has prefabricated cavities. Polysilicon TSV integration to C-SOI structure is also straightforward.   Important is that the wafer is CMOS-compatible and can be processed  in CMOS line without risks of cross-contamination.  Cavity can be very deep, e.g. allowing enough space for mirror tilt, and lateral dimensions can be up to several mm´s.  Figure 1. shows an example of inertial sensor made using C-SOI with a TSV.

C-SOI platform offers good possibilities for 3D-integration, and the assembly is easily thinable to meet current requirements for thin MEMS components. New manufacturing techniques allow very uniform device layers, < +/- 100 nm tolerances, even when device layer thickness is several tens of µm´s.

Bond interface quality and hermeticality of the structure is of key importance, and the long term reliability of the device e.g. in automotive applications has to be guaranteed. Therefore every wafer has to be measured with best possible means.  Bond surfaces and cavities are inspected with automated optical systems and bond integrity is measured with scanning acoustic microscopes. Challenge is to have proper balance with productivity and tool resolution – further development is needed with inspection tools, both inspection speed as well as resolution need improvements.

Presentation discuss briefly also on metal bonding and SOI structure using ALD-aluminum oxide instead of silicon dioxide as isolating layer.

Thur 11:30
Harald PreuInfluence of Sample Preparation on Intrinsic Stress inside a Model Chip

The given project is to benchmark typical preparation methods under the aspect of the influence of initial intrinsic stresses inside electronic components. Micro drilling – and laser-decapsulation in combination with plasma etching were chosen as preparation methods. Raman spectroscopy has been applied as well as the piezo resistive readout on a specifically designed model stress monitoring chip. The results of the analysis at each manufacturing step of the model chip and the first investigations of partial decapsulation will be presented.

Thur 11:50
Viorel DragoiRoom Temperature Oxide-Free Semiconductor Bonded Interfaces

Despite the fact it was first reported almost 30 years ago, room temperature oxide-free wafer bonding of semiconductor substrates is nowadays in focus for its benefits in combining different materials for optoelectronics, power and high temperature electronics or solar cells applications based on the electrical performance of the bonded interfaces. We report here about a new room temperature wafer bonding technique based on ion beam surface activation. Experimental results for wafer bonding of various materials will be presented (Si-Si, Si-Ge, Si-SiC, etc.) The challenges of this process as well as the specific metrology needs for process characterization will be reviewed.

Thur 12:10
Thomas NuyttenNanoscale Stress Measurements Using Raman Spectroscopy

Recently, nanofocused coupling of light into a periodic array of fins re-enabled Raman spectroscopy of deep-subwavelength structures, like for example high-mobility channels for finFET technology. This effect transforms the response of very thin and narrow structures from hardly detectable to the dominant feature in the Raman spectrum. We demonstrate how the combination of this phenomenon with selective TO and LO phonon excitation enables non-invasive, quantitative metrology of stress at the nanoscale, without the need for additional sample preparation. Anisotropic biaxial stress is measured along and across sGe finFETs with channel widths down to 20 nm.

Thur 12:30
David Poppitz, Andreas GraffNanobeam Diffraction for Residual Strain Analysis in Materials for Microelectronics

Residual stress in microelectronic device structures are caused by thermo-mechanical mismatch from thermal processing or external temperature loads during qualification testing or operation. Stress gradients could be the driving force for migration mechanisms or could cause cracking and interface delamination with related failure modes. Nano Beam Electron Diffraction (NBED) is an established and highly sensitive technique for local strain analysis in crystalline materials and can be applied for nm resolved strain mapping. The potential of NBED local strain field analysis will be shown for selected applications of semiconductor devices. Application of NBED strain mapping will be presented in selected case studies for GaN-HEMT migration at small scale Schottky gate contacts, GaN on Si wafer edge characterization after dicing and migration at photodiodes. This will help to identify related failure modes and to optimize growth parameters and design of devices.

Thur 12:50
Michael HeckerMechanical Integrity Analysis of Crack Stop Features in Chip Designs for 28nm and below

Crack initiation and propagation in BEoL (Back-End of Line) interconnect structures is a concern in terms of chip reliability and mechanical stability. Thus, dedicated techniques for the evaluation of mechanical parameters such as the fracture toughness are required. Typically, in such tests not only investigation of a random crack path but of specific structures affected e.g. by process variations is of interest. It will be shown how techniques such as 4pb (4-point bending), DCB (double cantilever beam bending) and MELT (modified edge lift-off test) can be adapted to characterize chip structures with respect to their mechanical stability. By combination with FEM simulations, effective approaches for directing the crack path into structures of interest during the mechanical tests were obtained.