Direct bonding is now a well-established technique that enables various 3D applications. Mass production of silicon dioxide to silicon dioxide bonding, as well as hybrid surfaces with copper pads, is in mass production within microelectronic foundries. However, hydrophilic direct bonding remains a challenging technology due to its very low adhesion energy, necessitating stringent control over surface properties such as flatness, roughness, and particle contamination. Before bonding, precise control of these surface parameters is mandatory.

Furthermore, post-bonding, it is imperative to monitor defectivity with a buried interface between 775µm of silicon. Bonding energy is also a crucial consideration, for which only destructive technology is currently available. Additionally, for in-depth analysis of the bonding interface, techniques such as X-ray, FTIR, or even neutron reflectivity are required.

While there are numerous failure analysis and surface material diagnostic methods at the wafer scale, the complexity significantly increases at the die scale, revealing vast challenges. As die-to-wafer bonding is on the verge of entering mass production, it is high time to extend the same characterization capabilities to this scale.

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NanoWired, founded in 2017 as a spin-off from TU Darmstadt, has developed and patented an interconnection technology known as the NanoWiring process. This process allows for the coating of various substrates with copper nanowires. From this foundation, several assembly processes have been derived: KlettWelding, KlettSintering, and KlettGlueing. The versatility of NanoWired’s technologies enables the connection of electronics across a wide range of contact sizes – from several square centimeters for power electronic parts down to microelectronic parts with contact diameters as small as a few micrometers. Remarkably, even highly sensitive components can be connected due to the ability to work at very low temperatures, including room temperature.

In this presentation, NanoWired will present the technology process flows and highlight its applications. Notably, the talk will delve into the use of NanoWired technology in GaN power electronics, exploring how flip chip technologies can enhance high-frequency behavior and reduce Rdson.

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Heterogeneous integration of chiplets enables complex and compact electronic systems by breaking the limits of reticle size. This is achieved by combining function-optimized wafer technologies with manufacturing yield improvements. Over the past few years, different 2.XD and 3D packaging architectures have been developed and introduced for high performance compute applications as well as commercial products. However, the complexity of such advanced package constructions leads to new challenges for managing the intrinsic mechanical stress as well as for adapted electrical test strategies. The presentation will give an overview of these challenges and how robustness can be improved and how product validation can be implemented.

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SSRM (Scanning Spreading Resistance Microscopy) is an established technique for 2D dopant visualization with high lateral resolution (~1-10nm) and sensitivity (~1E14-1E20 1/cm³). While normal SSRM produces qualitative information about doping shapes and sizes, quantitative SSRM adds a calibration measurement on a known dopant reference to extract absolute values on top. While this approach seems easy in theory, in actual practice one is met with numerous complications, often leading to a long and costly analysis. To alleviate such complications, we introduce two innovations: Firstly, we propose a novel Partial-Staircase (PSC) dopant reference profile which combines the advantages of the conventional staircase profiles and sole reference implants into one. Secondly an extended sample preparation workflow is presented, which brings area of interest and dopant reference into high proximity and enforces the exact same measurement conditions on both by design. Put together, both innovations reduce analysis complexity while increasing quantification accuracy.

Photonic integrated circuits (PICs) developed on silicon photonics (SiPh) platforms are a significant breakthrough in the field of data communication as they increase the speed and capacity of data transmission with lesser power consumption. It integrates devices such as lasers, photodetectors, optical waveguides, and modulators on the silicon substrate and can be fabricated using an industry-standard CMOS process. This has pushed SiPh devices into the commercial manufacturing phase. Hence, it is very relevant to perform the failure analysis (FA) to ensure the reliability of these devices. In my presentation, I will discuss the FA methodologies used for defect localization in emerging devices used in PICs such as photodetectors and laser diodes, fabricated at imec. In particular, germanium photodetectors and InGaAs/GaAs nano-ridge p-i-n diodes which are extensively researched and have the potential to be adapted in the industry, are used as test devices for this study. The application of conventional and advanced FA techniques such as lock-in thermography (LIT), thermoreflectance, and electron beam-based nanoprobing based on their spatial resolution will be discussed.

The FA Technology Roadmap initiative, which is driven by ASM’s Electronic Device Failure Analysis Society (EDFAS) Society, is actively involved to identify the longer term needs and gaps of failure analysis methods and equipment related to new trends in semiconductor device manufacturing. The purpose of the FA Technology Roadmap is to leverage the technical expertise captured throughout the industry to identify both current and future FA challenges and to serve as an international technical platform for failure analysis. The goal is to bridge existing and upcoming gaps by leveraging both the expertise of equipment providers and the research conducted in academic labs.

Last year, during the panel discussion, the invited panelists provided a summary of the progress made in the FA Technology Roadmap activities. They highlighted the ongoing efforts to identify and analyze the current and future FA challenges. This involved conducting an industry-wide gap analysis, which helped in mapping out the areas that require further attention and improvement.

This year, the focus is on the vendor’s responses to the industry-wide gap analysis survey. The committee is actively seeking input and feedback from equipment providers to gain insights into their perspectives on the identified gaps. This will enable the committee to gather valuable information on potential solutions and innovations that can address the challenges faced by the industry.

The FA Technology Roadmap Committee recognizes the importance of collaboration and knowledge-sharing between equipment providers, academic labs, and other stakeholders in the FA industry. By working together, they aim to drive advancements and improvements in FA techniques, tools and workflows.

Since its release, ChatGPT has sparked ongoing fascination for its human-like responses, reflecting the growing interest in AI’s potential applications across various fields. In microelectronics failure analysis, a discipline aiming for reliability and performance improvement, machine learning holds promise by aiding defect localization and subsequent analysis through destructive inspection tools. The ability to process large datasets and extract correlated information benefits defect analysis, assisting in identifying root causes.

This tutorial introduces machine learning and deep learning to failure analysts covering historical context, data handling, feature extraction, learning algorithms, model evaluation, and optimization. It explores convolutional neural networks for image processing and advanced neural network applications like auto-encoders and natural language processing. Case studies demonstrate ML’s potential in failure analysis, such as bill of material generation from optical images, automatic defect detection on PCBs, void segmentation in x-ray images, and SEM image denoising.

The implementation of wide band gap based power semiconductor solutions, was growing substantially during the last years, Driving forces behind this market development are global megatrends like energy saving, de-carbonization and effective use of scarce resources. One of the success factors of implementing SiC as a power device material is the chance to adopt many of the well-known device concepts and processing technologies from silicon.

Thus, many of the procedures used to verify the long-term stability of silicon devices could be transferred to SiC. Nevertheless, a deeper analysis has shown that SiC based devices require some additional and different reliability tests compared to Si based devices. Aspects like anisotropic material properties, higher electric fields or faster transients may have an influence on nearly all established qualification tests.

Furthermore, for many existing qualification standards that specify accelerated tests, models are used to extrapolate the test data and correlate it to real world application conditions. These model parameters need to be verified for their application and accuracy with respect to SiC. The keynote presentation will give a more detailed inside into the current status of SiC related reliability assurance
procedures, also addressing ruggedness aspects.

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Threshold voltage drift in MOSFET’s due to prolonged application of a high constant gate voltage at high temperature is a well-known degradation mechanism and has been observed in MOSFET-technologies based on silicon, gallium nitride, or silicon carbide.  A peculiarity of silicon carbide MOSFET’s is that high numbers of bipolar gate switching events result in a threshold voltage drift that exceeds the drift expected from constant voltage stress alone. The presentation will detail the properties of this degradation mechanism and will give an overview of possible root causes currently under discussion. Arguments to test worst case scenarios on chip level rather than on module level will be discussed.

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Nowadays, electrification trends, especially in the automotive market, are driving the need for high power electronics. In the past years, Silicon Carbide (SiC) and Gallium Nitride (GaN) microelectronics solutions have been introduced on the market as they have clear benefits for such application (its key benefits include delivering higher voltage operation, wider temperature ranges and increased switching frequencies). These Wide Band Gap (WBG) technologies are relatively new, thus, quality control and reliability understanding are critical topics to make sure they will remain sustainable.

We will present 3 Failure Analysis use cases and workflows related to power device technologies. In collaboration with our Fault Isolation tool equipment supplier (ThermoFisher Scientific), we have developed a High Voltage solution to address HV-O.B.I.R.Ch. and HV-Photoemission analysis on our Meridian S Platform. This solution allows addressing our current High Power devices roadmap up to 3kV.

Although not even mentioned in the original launch of the US materials genome initiative (MGI) in 2011, AI has now been identified the true enabler and driving force of MGI.Latest progress reports Google DeepMind and robots joined forces to discover and synthesis new materials. Microstructure of materials should be treated as a system as perceived by the pioneering work of C.S. Smith. Highlighting the achievements of MGI in the past decade, it is the atomic scale details represented by DFT-based calculations and graph neural network that have attracted most of the interests. Phase spaces that reflect elemental combinations to yield desirable chemistry or physics have been explored, but the results that AI recommends still deserve better interpretations. Based on a convergence amongst deep neural networks, wavelets, and physiology of human brain, and the theory of Mallat Scattering Transform, this talk introduces the principles behind the recent proposed Microstructure Hierarchy Descriptor (μSHD). The μSHDs are designable and reduced order indices that can be used to establish quantitative linkages between structures, properties, and failure analyses. Applied microstructure diagnostics spanning structures from electron to device levels, and failure analyses on 3D and power electronics will be discussed with a vision from μSHD data to microstructure informatics and AI.

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Microelectronic products from the semiconductor industry are crucial for many recent technological advances in automotive industries and intelligent production systems but have reliability issues that require failure analysis to investigate the failures’ root cause. Using visual inspection systems such as cameras or microscopes, images of microelectronic products or components are acquired to be evaluated for potential defects and anomalies arising from the manufacturing process. Manual evaluation of such a large amount of data carries the risk of subjective errors, consumes lot of time and efforts, leading to backlogs that can drive costs.

In this work, we developed defect detection models using advanced machine learning and computer vision approaches that are more reliable, with detection accuracy close to or sometimes better than manual or existing approaches. The developed models for different use-cases (voids, phases, anomalies), have an accuracy ranging from 86 % to 94 % and has advantage of being time-efficient by a factor of 20x to 30x for different tasks. Each use-case involves image data from various microscopy techniques such as OM, SEM, X-ray and SAM.

Physical failure analysis (physical FA) for automotive devices requires an efficient FA workflow to satisfy the customer’s expectations of on-time-delivery and success rate. Field return complaints typically contain only one single failing device. Hence, every step in fault isolation and physical preparation requires a high confidence level in order to avoid the risk of losing the failure in subsequent destructive steps.
We will present a software to support the FA engineer to quickly identify correct and incorrect logic signals in digital circuits enabling fast and successful FA.

In EU-funding project FA4.0, the idea of Integrated Workflows within FA has been defined and is being developed. Integrated Workflows in FA means that sample remains on the same sample holder in a whole workflow and data, especially position data of regions of interest, es being transported from tool to tool to simplify the workflows for the user as well as increase efficiency. To enable these workflows on tools of different vendors, exchange formats for data as well as a common universal sample holder has to be defined which is established also as industrial standard. This presentation will show an example how this principle can work including a TePLA-SAM and a Tescan-PFIB and also of the necessary standardization process in cooperation with SEMI.

The AFM-in-SEM approach combines Atomic Force Microscopy (AFM)-based techniques with Scanning Electron Microscopy (SEM)-based or Focused Ion Beam FIB-SEM based techniques. It provides a means to integrated correlative approach for studying semiconductor materials and devices. This solution allows for the non-destructive mapping of diverse electrical properties of trenches, measuring gate dimensions or localizing defects, which could help to understand the device processes. This approach provides the advantages of combining the benefits of capabilities of site-specific sample preparation by FIB, ultra high-resolution imaging by SEM and AFM techniques. The integration offers additional benefits, including measuring properties at the exact location under in-situ conditions and avoiding sample or environmental changes such as differential pressure or sample contamination. Typical example of such site specific analysis is dopant concentration profiling on the level of individual device.

In semiconductor electronics, efficient failure analysis is crucial for reliability. Here, we present an automated workflow for precise and rapid failure analysis. Optimizing probe placement significantly cuts analysis time while improving result reliability, which is particularly beneficial for beginner nanoprobing users.
In a proof-of-concept experiment, the probe alignment and landing process was successfully achieved through a few clicks. Our study demonstrates that this process can be successfully executed not only at high electron beam energy voltages but also at low electron beam voltages, ensuring versatility and robustness in failure analysis workflows.
Furthermore, our study introduces a semi-automated failure analysis workflow incorporating encoded micromanipulators for examining devices down to 3 nm. All this, coupled with advanced data processing integrated into the Kleindiek Advanced Probing Tool software and Electron Beam Induced Current (EBIC) analysis, enables comprehensive characterization of device failures. An automated workflow signifies a significant advancement in semiconductor failure analysis for improved reliability and innovation.