|Wed 09:50 – 10:30||Deepak Goyal||Keynote 1: Advanced 2D & 3D Packaging Architectures|
Heterogeneous Integration (HI) of disparate computing and communications functions is a key enabler of performance in micro-electronic systems. HI is crucially enabled by advanced packaging since packages are an optimal HI platform. This talk will address the role of advanced packaging in enabling HI and will focus primarily on the technology evolution of package interconnect densities. It will show how 2D and 3D packaging has evolved to provide increased interconnect density and key high end technologies such as EMIB, the silicon interposer and 3D stacking will be discussed in this context. This talk will also discuss challenges and opportunities in key areas such as interconnect scaling, power management, high speed IO, thermal management, test and FI/FA.
|Wed 10:30 – 11:10||Darvin Edwards||Keynote 2: TSV and FOWLP Reliability and FA Challenges|
Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two rapidly growing semiconductor package technologies with reliability risks based on their immaturity. Challenges for TSV reliability include Cu pumping, side wall dielectric cracking, Back-End-of-Line (BEOL) cracking, micro-bump fatigue and electromigration, wafer backside contamination, and thermal issues. FOWLP challenges include chip shifting, warpage, RDL reliability, and system level integrity under thermal cycling and shock environments. This talk briefly highlights contributing factors to these failure mechanisms and presents solutions. Failure analysis techniques and reliability assessments to insure reliability has been designed in during the package development process are detailed.