Abstracts by Session
Session C: Acoustic defect detection and micromechanical characterization methods
Wed 15:50 – 16:10
Stefan OberhoffGHz-SAM analysis approach for bondpad cratering

GHz scanning acoustic microscopy (GHz-SAM) was successfully applied for non-destructive evaluation of the integrity of back end of line (BEOL) stacks located underneath wire-bond pads. Due to the low penetration depth in the acoustic GHz regime, a specific sample preparation was conducted in order to provide access to the region of interest. Cratering related cracks in the bond pads were imaged clearly by GHz-SAM. The morphology of the visualized defects corresponded well with the results obtained by chemical cratering tests and by FIB cross-sections. Moreover, delamination defects at the interface between ball and pad metallization were detected and successfully identified.

Wed 16:10 – 16:30
Duy-Long LêParametric Signal Analysis of high resolution SAM

Daily business has shown the resolution for high-frequency C-Scans of thin silicon samples vary with different silicon thicknesses. The results are not only blurred C-Scans but artefacts like alternating brightness stripes (ABS) which appear for specific silicon thicknesses and warpage of the sample. In order to understand the appearance of the ABS and how optimized image quality is achieved, a MATLAB algorithm is developed that can automatically evaluate the measured C-Scans of a transducer in a way that the image resolution and contrast are determined for each silicon thickness relative to TOF. Based on the evaluation algorithm, the optimum bias for a 230 MHz and 200 MHz transducer is determined with silicon thicknesses of 170 μm and 75 μm.

Wed 16:30 – 16:50
Falk NaumannMicro-Transfer-Printing and its Process Characterization by FEA & Micromechanical Testing

Micro-Transfer-Printing (μTP) as an alternative micro-assembly technology opens up new possibilities in the integration and packaging of smart devices like processed III/V devices, optical filters and special sensors on CMOS and MEMS on wafer-level. The technology uses an elastomer stamp to manipulate multiple printable components at the same time. Nevertheless, the industrial application of this technology as well as the transfer and upscaling from laboratory scale is still challenging. In order to realize a reliable printing process with sufficient yield, the interaction of the components to be printed, their fixation by tether structures and the transfer properties must be well adapted. Therefore, the presented work will deal with results of mechanical experiments and FEA-modelling in order to get a deeper understanding of the μTP-process and potential failure modes.

Wed 16:50 – 17:10
Stefan SpäthCharacterization of Intermetallic Phases using High Speed Nano-Indentation

The given project shows an application of High Speed Nano-Indentation for characterization of solder alloys of electronic devices. Additionally, EDS analysis was performed to correlate the material properties with the single phases. This enabled a detailed description of the given solder alloys, which was provided to the simulation team who are trying to simulate the device’s thermal and electric behaviour to improve development time of new materials.

Wed 17:10 – 17:30
Dirk UtessTEM strain measurements and microstructure analysis semiconductor

The introduction of 22nm fully depleted silicon on insulator technology enables low power and low leakage chip designs. In addition this technology is also perfectly suited for high performance RF and mmWave applications. Therefore it is required to enhance the charge carrier mobility in the transistor channel. This can be achieved by Si/SiGe strain engineering. In order to understand the strain state in those very thin silicon films, it is key to characterize the local strain with high spatial resolution. Therefore two well established techniques PED (Precession Electron Diffraction) and NBD (Nano Beam Diffraction) were used to investigate transistor test structures. In addition to presenting strain state measurements results, ways to simulate strain in transistor architectures will be discussed.