Abstracts by Session
Session D: Fault Isolation
Thur 08:30 – 09:10
Sven BeyerTrends non-volatile memory technology and FA

The power efficiency of neural networks is currently limited by the von-Neumann bottleneck as well as the high standby power of near compute memory. Keeping data storage and data transfer digital for reproducible network deployment, a new type of non-volatile memory is needed. Ideally circuit designers are looking for a non-volatile memory that combines unlimited endurance, digital data storage, flexible single cell intermix-ability with standard CMOS logic, high dynamic range, low switching power and acceptable cost in advanced CMOS technology nodes. Currently there is no ideal memory solution in sight, but several emerging memories offer significant advantages over the proven eNVM-working-horse eFLASH. Among those are eMRAM and ferroelectric FETs. Especially the FeFET technology is going to be introduced and discussed in detail.

Thur 09:10 – 09:30
Szu Huat GohSignificance of multi-level circuit trace Analysis for Design Debug

As we operate under escalating time pressures to deliver faster product time-to-market, it is necessary to constantly re-examine and improve on the custom failure debug process to shorten the turnaround time. This work studies the limitations of current commercial first-level net trace capability when using design GDS to interpret the impact of localized signal hotspots and determine the region for physical inspection. We present a multi-level methodology that enables net tracing beyond first-level transistors. This is achieved using modular standard verification rules, also commonly known as design rule check (DRC) in design verification. This approach is extremely useful in the attempt to relate multiple signal spots from dynamic photon emissions or dynamic laser stimulations.  This work also highlights the importance of integrating cross-domain knowledge to advance failure analysis.

Thur 09:30 – 09:50
Luc SauryUse of Analog Simulation in Failure Analysis: Application to Emission Microscopy and Laser Voltage Probing Techniques

A new flow using analog simulations for the failure analysis of digital, analog and mixed signal devices is presented. It overcomes the actual limitations in failure analysis capabilities when dealing with analog IP’s or defects at transistor level.The flow consists of computing internal currents and voltages in digital or analog cells in order to interpret light emission and LVP results obtained on a physical device. It also allows to induce a defect and compare the simulated fault model with the experimental results collected on a fault isolation tool, which enables failure analysts to validate or invalidate fault hypotheses.

Thur 09:50 – 10:10
Venkat-Krishnan RavikumarUnderstanding crosstalk during laser probing at spatial resolution compromised technology nodes

Laser probing using NIR lasers at sub-20nm technology has become increasingly difficult due to interaction of the optic probe with multiple transistors. Laser probing waveform is the cumulation of modulations from every active transistor within the optic probe. When multiple transistors are active, they result in “crosstalk” or waveform corruption, resulting in misleading results. In this paper, we address some of the typical manifestations of crosstalk and corresponding mitigation strategies for successful probing at resolution compromised technology nodes.

Thur 10:10 – 10:30
Grigore MoldovanHigh resolution resistance mapping with in-situ EBAC nanoprobing

This work presents an overview and an update on resistance mapping in Scanning Electron Microscopy (SEM) using Electron Beam Absorbed Current (EBAC) signals acquired with nanoprobing systems. Recent advances include integration into the nanoprobing platform of dedicated in situ electronics to minimise noise and increase speed, as well as a transition to voltage sensitive amplification to improve resistance sensitivity beyond the 10 Ohms range, and to allow for mapping of resistors as low as 100 Ohms.

Thur 10:30 – 10:50
Yoshihiro Ito Two analysis methods for fault localization: SOBIRCH and OPTIM

We introduce two examples of analysis methods for fault localization.


SOBIRCH: IR-OBIRCH is a well-established technique used for die-level fault localization.  The technique uses an NIR laser source to cause localized heating, but is limited to die-level analysis because the NIR light cannot penetrate through packaging materials and mold compounds.  ultraSonic OBIRCH uses focused, ultrasonic stimulation (similar to C-SAM) to penetrate through the packaging material and induce the resistance change.  This approach allows for package-level OBIRCH analysis.  The paper will describe evaluation results on actual packaged ICs.


OPTIM: Thermoreflectance is a technique that uses the temperature dependency of the reflectivity of a sample to detect changes in temperature and identify hot spots.  Because the technique uses shorter wavelength laser light (e.g. NIR), it is a high resolution alternative to traditional lock-in thermography (LIT), which uses MWIR light.  Incidentally, the same hardware – NIR laser microscope, objective lenses, SIL – used for optical voltage probing (EOP/EOFM), can also be used to take thermoreflectance measurements.  This paper will present thermoreflectance evaluation results using EOP/EOFM hardware and comparisons with LIT.