KEYNOTES

1. Keynote

Deepak Goyal, Intel Corporation (US)
„Advanced 2D & 3D Packaging Architectures ”

Heterogeneous Integration (HI) of disparate computing and communications functions is a key enabler of performance in micro-electronic systems.  HI is crucially enabled by advanced packaging since packages are an optimal HI platform.  This talk will address the role of advanced packaging in enabling HI and will focus primarily on the technology evolution of package interconnect densities.  It will show how 2D and 3D packaging has evolved to provide increased interconnect density and  key high end technologies such as EMIB,  the silicon interposer and 3D stacking will be discussed in this context. This talk will also discuss challenges and opportunities in key areas such as interconnect scaling, power management, high speed IO, thermal management, test and FI/FA.

Deepak Goyal graduated with a PhD from State University of New York, Stony Brook, and joined Intel as a Failure Analysis Engineer. He is currently the Director of the Assembly and Test Technology Development Failure Analysis Labs at Intel. His responsibilities include development of the next generation of analytical tools and techniques, defect characterization, fault isolation, failure and materials analyses for the next generation package technology development at Intel, analytical chemistry labs in support of the substrate development and manufacturing, and Board and System level failure analysis. He has won two Intel Achievement Awards and has several patents.

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2. Keynote

Darvin Edwards – Edwards Enterprises (US)
“TSV and FOWLP Reliability and Failure Analysis Challenges”

Through Silicon Via (TSV) and Fan Out Wafer Level Packages (FOWLP) are two rapidly growing semiconductor package technologies with reliability risks based on their immaturity.   Challenges for TSV reliability include Cu pumping, side wall dielectric cracking, Back-End-of-Line (BEOL) cracking, micro-bump fatigue and electromigration, wafer backside contamination, and thermal issues.  FOWLP challenges include chip shifting, warpage, RDL reliability, and system level integrity under thermal cycling and shock environments.  This talk briefly highlights contributing factors to these failure mechanisms and presents solutions.  Failure analysis techniques and reliability assessments to insure reliability has been designed in during the package development process are detailed.

Mr. Darvin Edwards has 39 years of experience in the IC packaging industry.  He currently owns Edwards’ Enterprise Consulting LLC which specializes in helping companies solve package reliability problems as well as providing worldwide training on topics such as package reliability, package materials, surface mount technologies, and package thermal, mechanical, and RF design.  He worked 33 years at Texas Instruments, becoming a TI Fellow, managing the Dallas modeling and simulation team as well as FA development.  Mr. Edwards has authored and co-authored over 65 papers and articles, has written two book chapters, and holds 24 US patents.

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3. Keynote

Sven Beyer, Global Foundries (DE)
„Neuromorphic Computing as Driver of the Diversification of the Embedded Non-Volatile Memory Landscape”

The power efficiency of neural networks is currently limited by the von-Neumann bottleneck as well as the high standby power of near compute memory. Keeping data storage and data transfer digital for reproducible network deployment, a new type of non-volatile memory is needed. Ideally circuit designers are looking for a non-volatile memory that combines unlimited endurance, digital data storage, flexible single cell intermix-ability with standard CMOS logic, high dynamic range, low switching power and acceptable cost in advanced CMOS technology nodes. Currently there is no ideal memory solution in sight, but several emerging memories offer significant advantages over the proven eNVM-working-horse eFLASH. Among those are eMRAM and ferroelectric FETs. Especially the FeFET technology is going to be introduced and discussed in detail.

Dr. Sven Beyer received his masters degree and phD in semiconductor physics from the Hamburg University. Since then he spent over 15 years in the semiconductor industry, with responsibilities ranging from unit process manufacturing, to technology development in the integration department and customer engineering. He has worked for Infineon Technologies, AMD and GLOBALFOUNDRIES in Dresden and spent over a year in the IBM ASTA technology alliance in Fishkill NY. Sven holds over 130 patents in the field of CMOS based technologies and has worked on technology nodes ranging from 180nm down to 22nm. Currently Sven is a senior manager & deputy director at GLOBALFOUNDRIES FAB1 Dresden and heading the TD group for embedded non-volatile memories.

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