|Tues 10:40 – 11:00||Viorel Dragoi||Hybrid wafer bonding for 3D integration: promises and challenges|
Over the past decade wafer bonding technology was adopted for an increasing number of applications due to the unique solutions provided for wafer-to-wafer, as well as for die-to-wafer integration. Besides fusion wafer bonding, hybrid wafer bonding is offering major technical benefits in the fabrication of 3D architectures.The process is extremely challenging in terms of substrates preparation, as substrates must accommodate two types of bonding processes simultaneously (dielectric-dielectric low temperature fusion wafer bonding and Cu-Cu thermo-compression wafer bonding). The continuous device features shrinking additionally brings constant challenges to the users. Some of the main challenges of this technology will be reviewed with respect to process specifications and the importance of new metrology and investigation methods adoption will be emphasized.
|Tues 11:00 – 11:20||Kristof Jacobs||Failure Analysis Approaches for Test Structures Targeting Wafer-to-Wafer Hybrid Bonding and Backside Power Delivery Development|
In the field of three-dimensional (3D) integration, the introduction of hybrid bonding and backside power delivery has brought new opportunities to reduce the 3D interconnect pitch below 2 μm and logic scaling beyond the 5 nm technology node. In this presentation, we report failure analysis (FA) approaches for the localization of process-induced defects on test structures used for the research and development phase. We show how a local substrate removal process enables the localization of defective wafer-to-wafer (W2W) interconnects with a pitch of 700 nm using laser scanning techniques; and we demonstrate the use of conductive atomic force microscopy (C-AFM) for imaging the electrical connectivity of a backside power delivery network.
|Tues 11:20 – 11:40||William Lo||X-Ray Device Alteration Using A Scanning X-Ray Microscope|
The increasingly widespread adoption of 3D packaging for Heterogeneous Integration, and the upcoming IC architectural shift to backside power delivery networks presents unprecedented challenges to the FA community. Intervening NIR-opaque layers obsoletes or severely limits the usefulness of some of the most widely used techniques developed and refined for flip-chip ICs over the past few decades. Techniques such as LVP and LADA will no longer be generally applicable, while techniques such as SDL and LIT will be severely compromised. The FA community must find alternatives to fill as many of the gaps as possible. Techniques capable of penetrating NIR-opaque materials, such as those based on thermal effects, magnetic fields, or X-rays, are of great interest. In this talk, I will present our recent work investigating the potential for using X-rays for targeted and intentional device alterations, with the goal of finding a suitable substitute for LADA. X-ray Device Alteration results from an isolated nFET in a 5-nm flip-chip IC will be presented. The effects will be compared and contrasted to those obtained using a 1064-nm laser.
|Tues 11:40 – 12:00||Sebastian Brand||Advances in high-resolution nondestructive defect localization based on recent developments in signal processing|
The increasing level of assistance and automation not only in the mobility sector demands a high reliability of increasingly complex microelectronic components and systems. To ensure the required performance and the necessary safety evolving technologies need to be understood in their behaviour down to the formation and propagation of defects and the interaction of the involved materials under operational conditions. In this respect capable testing and inspection techniques are required for analysis, but also for screening during production processes to maintain high quality levels, which is connected to large quantities of data. The paper describes the application of deep learning techniques for enhancing the analysis of acoustic time-domain signals for decision making and material characterization. Microelectronic systems commonly contain complex structured architectures. Unfortunately, this complexity and the correspondingly large number of material interfaces and their small dimensions result in the occurrence of multiple overlapping pulses in the received signals, challenging accurate interpretation. However, the obtained signals precisely represent the interaction of the acoustic wave with the samples. Machine learning is employed here to optimize time-domain signals and extract characteristic to non-destructively obtain information which is related to physical properties of the sample under investigation and consequently detect and precisely localize defects.
|Tues 12:00 – 12:20||Harald Gossner||ESD Targets and Test Methods for High Density Die-to-Die Interfaces|
To drive Moore’s Law forward semiconductor industry is now entering a fourth evolution phase using massive heterogenous integration, which allows to integrate novel functionality of an IC at best power-performance and lowest cost on package level. A key element for integrating various dies into one package are die-to-die interfaces which will amount to the millions per package. This requires a reconsideration of typical ESD robustness targets for interfaces. Assuming same charged device model (CDM) targets of interfaces connected to the much lower number of package balls would lead to an exploding use of die area. Also, the limited exposure to ESD thread in only a few of process steps allows to lower the targets to 5 V CDM and below for die-to-die interfaces. Industry Council on ESD Target Levels is providing guidance to practical CDM targets in a recent White Paper which will be discussed in the presentation.