Over the past decade wafer bonding technology was adopted for an increasing number of applications due to the unique solutions provided for wafer-to-wafer, as well as for die-to-wafer integration. Besides fusion wafer bonding, hybrid wafer bonding is offering major technical benefits in the fabrication of 3D architectures.The process is extremely challenging in terms of substrates preparation, as substrates must accommodate two types of bonding processes simultaneously (dielectric-dielectric low temperature fusion wafer bonding and Cu-Cu thermo-compression wafer bonding). The continuous device features shrinking additionally brings constant challenges to the users. Some of the main challenges of this technology will be reviewed with respect to process specifications and the importance of new metrology and investigation methods adoption will be emphasized.

In the field of three-dimensional (3D) integration, the introduction of hybrid bonding and backside power delivery has brought new opportunities to reduce the 3D interconnect pitch below 2 μm and logic scaling beyond the 5 nm technology node. In this presentation, we report failure analysis (FA) approaches for the localization of process-induced defects on test structures used for the research and development phase. We show how a local substrate removal process enables the localization of defective wafer-to-wafer (W2W) interconnects with a pitch of 700 nm using laser scanning techniques; and we demonstrate the use of conductive atomic force microscopy (C-AFM) for imaging the electrical connectivity of a backside power delivery network.

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