Circuit netlist recognition is an important step in the analysis flow of hardware assurance. The main objective in circuit netlist recognition is to classify circuit netlists into different categories according to their structural differences for the purposes of design verification and trojan detection. Traditional methods are usually based on human knowledge and statistical heuristics, which incur a large degree of error and cannot easily handle large ASIC circuit netlists. In this paper, we propose a machine learning solution based on graph neural network for automated circuit classification. By performing experiments on example synthesized ASIC circuits, we showed that our machine learning model produces highly accurate predictions of 98.3% accuracy.

In recent years, the design rules of more advanced LSI’s has reached the nanometric scale, and spatial resolution provided by infrared light has become too weak. One of the path to overcome this bottle neck, consists to use shorter wavelength even by facing the barrier of the absorption edge of the Silicon. The success rate of this method is conditioned by ability to ultra thin the Si substrate, by keeping the device operational but ultra thinning still far to be an ideal solution practically. In this paper, we propose a method to limit the thinning complexity and use a 930 nm incoherent light source to improve spatial resolution as close as possible as visible light would do, without facing issues met with visible light on EOP ( Laser Probing ) waveform signal amplitude. The combination of this 930 nm light source with a specific new designed Solid Immersion Lens ( Nanolens X ) will be also explained.

The ability to isolate or expose faulty circuits, drives new technology and applications in the Electrical Failure Analysis industry. Electrical failure analysis systems are a workhorse in many labs as they provide a comprehensive capability to isolate a defect from a 1mm range down to sub-micron range, spatially. Additionally, some systems are capable of also providing high temporal resolution.  However, due to  the aggressive scaling of logic transistors to single digit gate widths, there is clear need for a better timing information and spatial resolution.  Two new advancements, Time Resolved-Laser Assisted Device Alteration (TR-LADA) and Electron Beam (E-beam) probing have recently been developed to address the needs of next generation semiconductor devices. This talk will review the technologies and provide insights into their applications on advance logic integrated circuits.

In the quest for ever more efficient and performant devices, the structure sizes of individual transistors keep shrinking. Identifying and analyzing faults on these devices is becoming more and more challenging. For example, previous investigations show that using typical beam acceleration voltages of 500 V and above may affect the transistors being investigated and thus hiding the underlying issue that is being investigated.

The result is a need for high resolution imaging at very low beam acceleration voltages of 100 V or below. When working at low beam acceleration voltages, the entire setup must be taken into account, starting from fields generated by the electron microscope depending on the chosen settings, in addition to the geometry and setup of the probing system and the workflow regarding probe approach and touchdown.

In order to overcome these issues, nanomanipulators with integrated positional encoder can be utilized in order to arrange the probes as described without irradiating the sample. In this work, a low-kV nanoprobing workflow will be described and the results from probing experiments on a current device, manufactured in 5 nm technology, will be discussed.