Abstracts by Session
|Tues 10:40 – 11:00||Viorel Dragoi||Hybrid wafer bonding for 3D integration: promises and challenges|
Over the past decade wafer bonding technology was adopted for an increasing number of applications due to the unique solutions provided for wafer-to-wafer, as well as for die-to-wafer integration. Besides fusion wafer bonding, hybrid wafer bonding is offering major technical benefits in the fabrication of 3D architectures.The process is extremely challenging in terms of substrates preparation, as substrates must accommodate two types of bonding processes simultaneously (dielectric-dielectric low temperature fusion wafer bonding and Cu-Cu thermo-compression wafer bonding). The continuous device features shrinking additionally brings constant challenges to the users. Some of the main challenges of this technology will be reviewed with respect to process specifications and the importance of new metrology and investigation methods adoption will be emphasized.
|Tues 11:00 – 11:20||Kristof Jacobs||Failure Analysis Approaches for Test Structures Targeting Wafer-to-Wafer Hybrid Bonding and Backside Power Delivery Development|
In the field of three-dimensional (3D) integration, the introduction of hybrid bonding and backside power delivery has brought new opportunities to reduce the 3D interconnect pitch below 2 μm and logic scaling beyond the 5 nm technology node. In this presentation, we report failure analysis (FA) approaches for the localization of process-induced defects on test structures used for the research and development phase. We show how a local substrate removal process enables the localization of defective wafer-to-wafer (W2W) interconnects with a pitch of 700 nm using laser scanning techniques; and we demonstrate the use of conductive atomic force microscopy (C-AFM) for imaging the electrical connectivity of a backside power delivery network.
|Tues 11:20 – 11:40||William Lo||X-Ray Device Alteration Using A Scanning X-Ray Microscope|
|Tues 11:40 – 12:00||Sebastian Brand||Advances in high-resolution nondestructive defect localization based on recent developments in signal processing|
|Tues 12:00 – 12:20||Harald Gossner||ESD Targets and Test Methods for High Density Die-to-Die Interfaces|
To drive Moore’s Law forward semiconductor industry is now entering a fourth evolution phase using massive heterogenous integration, which allows to integrate novel functionality of an IC at best power-performance and lowest cost on package level. A key element for integrating various dies into one package are die-to-die interfaces which will amount to the millions per package. This requires a reconsideration of typical ESD robustness targets for interfaces. Assuming same charged device model (CDM) targets of interfaces connected to the much lower number of package balls would lead to an exploding use of die area. Also, the limited exposure to ESD thread in only a few of process steps allows to lower the targets to 5 V CDM and below for die-to-die interfaces. Industry Council on ESD Target Levels is providing guidance to practical CDM targets in a recent White Paper which will be discussed in the presentation.