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As the rapid evolution of semiconductor technologies brings many challenges to the failure analysis world, there is also a need for innovation in Die-Level Post-Isolation Failure Analysis. A Die-Level Roadmap Council of EDFAS (ASM International) has developed a roadmap to consolidate challenges & solutions for the post-isolation domain. The presentation will discuss the status of this roadmap.

The semiconductor industry is now relying on breakthrough innovation and investment in advanced packaging as silicon technology scaling encounters barriers moving forward. 3D or advanced microelectronic packaging is the industry trend to meet the ever-increasing market demand for increased performance, reduced power consumption, smaller footprint, lower cost, and integration of heterogeneous devices.  Innovations in Package Failure Analysis is critical to the success of advanced packaging technology development by providing timely feedbacks and solution paths to device yield issues or reliability test failures. The high level of functional integration and the complex package architecture in advanced 3D packages pose a significant challenge for conventional Fault Isolation (FI) and Failure analysis (FA) methods. In addition, the high-volume manufactory requires an innovative FA flow which is cost-saving, feasible of supporting high volume products, and with short Through Put Time (TPT). The EDFAS FA Technology Roadmap presentation from PACKAGE INNOVATION ROADMAP COUNCIL (PIRC) highlights recent innovations, technology gaps, and future development trends in Package FI and FA, including three main categories: 1) Artificial Intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

The FA Future Roadmap Council (FAFRC) is concerned the with identifying the longer term needs of the FA community. There is a continuous effort to improve FA tools but with every new node introduced, the requirements are increased resulting in a seemingly never-ending cycle of advancements. There are gaps identified in the FAFRC roadmap that do not have a solution at present but they may be bridged with advancements of existing technologies or new technologies not currently serving the FA market. Shorter term roadmaps are also being published by other FA Roadmap Councils.

The FAFRC roadmap has 6 common elements between logic devices, memory devices and packaging:

• Increase in complexity by expanding into the third dimension (3D)
• Introduction of new materials
• Continued but slower dimensional scaling
• Chip-package co-design necessary to realize performance benefits
• Automation, and
• Machine Learning (AI)

In this presentation we will share the findings of the FAFRC on work concluded in 2022. The effort is currently in phase 2.