Technology advances in electronic packaging have supported Moore’s Law and has become an enabler of product performance. The need for increased integration and market differentiation results in a diverse set of 2.5/3D packaging architectures requiring new materials, technologies, and manufacturing processes.

The area of high-performance heterogeneous integration will continue to require significant improvements in the collaterals required to enable time-sensitive, cost-effective technologies. This includes appropriate metrology tools and methods, and techniques for the analysis, characterization, and optimization of manufacturing and test process.

Novel sensors, data analytics and measurement standards to address feature size scaling and multi-material systems/interfaces are critical for fundamental quantification and understanding. Applications in the areas of process development, materials characterization, and performance validation, ranging across structural reliability, signal integrity, and thermal dissipation will be reviewed. New interconnect architectures such as optical co-packaging and the need for new competencies to meet future challenges will also be discussed.

In advanced CMOS technology, 2D scaling to provide power/performance gains together with area reduction is now seriously facing routing obstruction and back-end of line (BEOL) congestion. In other words, the latest node generations struggle to keep power/performance intact while scaling feature sizes. Scaling bottleneck considerations start to shift to the System-on-Chip (SoC) infrastructure aspects, and one specific booster that is addressed here is how to enhance the power delivery within a chip. We explore the concept of nano-TSV combined with buried power rail (BPR) and its extension to backside power grids as a system innovation that can largely provide the power–performance-area-cost (PPAC) benefits expected from technology scaling. Various Power Delivery Network (PDN) architectures are going to be discussed as industry is now picking up quickly the way to heterogeneous innovations in order to maintain the scaling roadmap for next generation ICs.

It is expected that Backside-PDN integration will bring new challenges to metrology and failure analysis.  Controlling the extreme wafer thinning process and the high precision back-to-front lithography overlay requirements challenges the current metrology techniques.  The proximity of nTSV to active devices may also result in novel requirements for reliability studies.

In this presentation we will focus on the physical inspection methods, attacks, reverse engineering techniques, and counterfeit electronics from the device to system level. With hardware being at the heart of the communication and networking systems, it is paramount to understand it’s security and the vulnerabilities. This talk presents how advanced microscopy, failure analysis (FA) techniques combined with image analysis and machine learning can provide assurance to electronics systems and set the stage for secure microelectronics hardware.

Dr. Navid Asadi is an Assistant Professor in the ECE Department at the University of Florida. He investigates novel techniques for IC counterfeit detection and prevention, system and chip level decomposition and security assessment, anti-reverse engineering, 3D imaging, invasive and semi-invasive physical assurance, supply chain security, etc. Dr. Asadi has received NSF CAREER award and several best paper awards from IEEE International Symposium on Hardware Oriented Security and Trust (HOST) and the ASME International Symposium on Flexible Automation (ISFA). He was also winner of D.E. Crow Innovation award from University of Connecticut. He is co-founder and the program chair of the IEEE Physical Assurance and Inspection of Electronics (PAINE) Conference.